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PIC18F1230/1330
DS39758D-page 98
2009 Microchip Technology Inc.
11.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2 and PIR3).
Note 1:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state
of its corresponding enable bit or the Glo-
bal
Interrupt
Enable
bit,
GIE
(INTCON<7>).
2:
User
software
should
ensure
the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 11-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
U-0
R/W-0
R-0
R/W-0
—
ADIF
RCIF
TXIF
CMP2IF
CMP1IF
CMP0IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented:
Read as ‘0’
bit 6
ADIF:
A/D Converter Interrupt Flag bit
1
= An A/D conversion completed (must be cleared in software)
0
= The A/D conversion is not complete
bit 5
RCIF:
EUSART Receive Interrupt Flag bit
1
= The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0
= The EUSART receive buffer is empty
bit 4
TXIF:
EUSART Transmit Interrupt Flag bit
1
= The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0
= The EUSART transmit buffer is full
bit 3
CMP2IF:
Analog Comparator 2 Flag bit
1
= The output of CMP2 has changed since last read
0
= The output of CMP2 has not changed since last read
bit 2
CMP1IF:
Analog Comparator 1 Flag bit
1
= The output of CMP1 has changed since last read
0
= The output of CMP1 has not changed since last read
bit 1
CMP0IF:
Analog Comparator 0 Flag bit
1
= The output of CMP0 has changed since last read
0
= The output of CMP0 has not changed since last read
bit 0
TMR1IF:
TMR1 Overflow Interrupt Flag bit
1
= TMR1 register overflowed (must be cleared in software)
0
= TMR1 register did not overflow
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